Conventional EEPROM cells have a single EEPROM transistor that represents a single bit of data by storing a voltage charge. The transistor is charged or discharged during a programming (write) operation. The transistor is then read during a read operation by coupling the source or drain of the EEPROM transistor to a sense amplifier which compares the charge on the EEPROM transistor to a reference voltage.
Sierra Semiconductor Corporation discloses an EEPROM cell (Electronics, Mar. 17, 1986, pp. 30-34) that utilizes a CMOS latch (flip-flop) with dual EEPROM transistor switches. The dual EEPROM transistor switches represent a bit by one EEPROM transistor being charged and the other not or vice versa. A differential latch detects the difference in charge between the EEPROM transistor switches, thereby determining the value stored in the EEPROM cell.
Because a high voltage on the drain will cause data errors, the supply voltage for the Sierra EEPROM cell must be within a 0 volt to approximately 6 volt range. Furthermore, Vcc must be pulsed during read because of the differential latch. Therefore, the access time needed to read the EEPROM cell is increased by the pulse time. In addition, parasitic capacitance and unequal noise coupling can cause an inaccurate read at the EEPROM cell due to transients caused by the pulse. Furthermore, the read and write circuits for the EEPROM device are separated for control over and protection of the EEPROM cells.